1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit which controls a power supply voltage for the purpose of reducing power consumption.
2. Description of the Related Art
In Semiconductor integrated circuits, and battery-driven portable terminals in particular, it is required to reduce power consumption. In order to reduce power consumption, clock signals are conventionally suspended by use of a gated clock method. With the development of the semiconductor process technology, processors or the like are now manufactured with fine patterns smaller than 0.13 micrometers. With such fine patterns., leak currents that were conventionally treated as errors may account for a substantial proportion that cannot be disregarded. Leak currents flow all the time regardless of the active/inactive state of processors, and cannot be suppressed by the gated clock method that suspends clock signals. When the processors or the like are in the standby state, in particular, leak currents continue to flow despite the suspension of clock signals unless the internal voltage inside the chip is suppressed.
In consideration of the influence of leak currents, some methods are beginning to be employed that suspend the supply of an internal operating voltage except for a portion of a power-supply control circuit or the like inside a chip when the processor is put into a standby state. Patent Document 1, for example, discloses a circuit configuration in which the sequential circuits of a CPU and core circuitry are implemented by use of a plurality of flip-flops and a plurality of combinatorial circuits permitting scans. In order to reduce the leak currents of the data processing device in a standby mode, the data stored in the flip-flops are saved through scan chains to a ferroelectric memory under the control of a control circuit before a transition is made from a normal mode to the standby mode. Further, Patent Document 2 discloses a configuration in which memory devices constituting the registers of a microcomputer are implemented by use of nonvolatile memories that are over-writable. In this configuration, the supply of a power supply voltage is suspended without evacuating data stored in the registers.
Moreover, Patent Document 3 discloses a technology that does not control power supply, but that is relevant as it relates to a booting method. The disclosed technology relates to a configuration in which booting is performed by referring to the contents of a nonvolatile memory, and recovery to a desired program state is achieved from any program execution state in response to the contents of the nonvolatile memory without going through a reset sequence. Further, Patent Document 4 discloses a configuration in which the areas of an on-chip nonvolatile memory are segregated so that the protocol codes of user-dedicated communication are not destroyed even when the computer goes out of control.    [Patent Document 1] Japanese Patent Application Publication No. 10-78836    [Patent Document 2] Japanese Patent Application Publication No. 2004-78772    [Patent Document 3] Japanese Patent Application Publication No. 2002-297563    [Patent Document 4] Japanese Patent Application. Publication No. 2002-297561
The technology described in Patent Document 1 requires a special configuration for evacuating and recovering registers by use of scan chains dedicated for register evacuation. This present a problem in that the circuit of a CPU core or the like having already been developed cannot be utilized. It may be plausible to save the contents of registers to an external SDRAM or nonvolatile memory. Since access to a memory device external to the chip is slow compared to access to a memory inside the chip, however, the evacuation and recovery of register data requires a lengthy processing time.
In order to keep the influence of leak current to a minimum, some methods are beginning to be employed that lower an internal operating voltage to reduce leak currents during a period in which the processor or the like does not need to operate at high speed, and that raise the internal voltage during a period in which high-speed operation is required. In such a case, there is a risk of the processor suffering a hangup as it becomes incapable of executing instructions due to internal voltage reduction. In consideration of this, vital register data and the like are saved to an external memory in advance. Upon a hangup, the CPU core or the like is initialized, and the saved register data and the like are recovered to permit a continued operation. Even in such case, however, access to a memory device external to the chip is slower than access to a memory inside the chip, thereby requiring a lengthy processing time for the evacuation and recovery of the register data.
Accordingly, there is a need for a semiconductor integrated circuit that allows various register values to be readily saved and recovered at high speed when a standby state for suspending the supply of an internal operating voltage or a state for lowering an internal operating voltage is put into effect.